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2.0 Introduction

2.1 Overview

The development of very large scale integrated circuits has made possible the creation of digital signal processing microprocessors. This class of microprocessor can perform task that formally could only be done using analogue devices. Analogue television, when first introduced, transmitted and received data using analogue components only, but today analogue television receivers and transmitters use an increasing amount of digital signal processing technology. This project is an investigation into the development of a digital signal processing system, designed to receive and display analogue television signals.

Shown below is an illustration of the complete system.

2.2 PAL decoder

Pal is a video standard adopted in the United Kingdom around the end of the 1950's. It is a method by which a colour signal can be transmitted using minimal bandwidth and also allowing monochrome receivers to receive and display a monochrome signal. The main feature of the PAL system is the alternating line. A PAL signal comprises a luminance signal, which is the sum of the red, green and blue values taken from a colour video source, and a chrominance signal, which comprises two more signals, the difference between the luminance and the blue signal and the difference between the luminance and the red signal. The two components of the chrominance signal are combined using quaderature amplitude modulation (QAM),where by the signals are modulated with separate carrier signals which are 90 degrees out of phase and of equal frequency and amplitude. The resultant signals are then added together. The QAM modulated signal is added to the luminance signal and transmitted. However in order to demodulate the transmitted signal two coherent demodulation signals are required. These are generated by adding a phase reference to be beginning of each line transmitted. The phase reference is then used by a PLL in the receiver to synchronize the demodulating signals. However interference can cause a shift in phase of the QAM signal component when it transmitted, so when it is demodulated there will be phase error. If the noise affects the QAM image data but not the reference burst then the color pallet will change mid line. This problem is resolved by alternating the phase of the transmitted QAM signal on alternate lines. Therefore in transmission, if distortion causes the QAM phase to be shifted by 3 degrees at a given point on a line and if the QAM is phase reversed on the next line then the error at the same point on the next line will be -3 degrees. By taking the average of the two lines the net result is an error of 0 degrees. Ref[3,PAL,11.10]

See Appendix F for Phase Alternate Line detail.

 

2.3 Microprocessor

The microprocessor is mounted on a PCB board containing the boot ROM and serial interface hardware to allow the TMS320 to be programmed "in circuit" by using TMS320 compatible debugging software on a PC.

The TMS 320 DSP microprocessor is optimised for doing DSP type operations. This is done by making the TMS320, especially good at operations such as addition, multiplication and using lookup tables. The TMS can multiply, add, increment a pointer to data and then select another data table all in one 50ns clock cycle. This allows it to process data at the same rate as a much more expensive and faster microprocessor.

The processor also has a repeat instruction that will cause a series of instructions to be repeated, however when the repeated instructions are executed, they are optimised, requiring fewer clock cycles to execute the instructions, thus speeding up the data processing even further.

See Appendix I 1-2 for an illustration of the microprocessor circuit design.

The TMS320 can access 64K of external data using the parallel port. The parallel port, when used with the address bus can be allowed to access 16 different ports. An address decoder is used on the address bus, where the output of the address decoder asserts one of 16 tri state buffers on the parallel port. Ref[1]

See Appendix E2 for an illustration of a memory address decoder.

 

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