4.0 Hardware Design
4.1 Introduction
The hardware is a basic
sampling system. An analogue television signal is converted into digital information,
which is then stored in SRAM. The SRAM and sampling process is controlled
by a control unit.
PAL specifications state
that one complete line scan takes 64us. With a sampling rate of 20MHz and
memory capacity of 128KByes the number of lines that can be sampled is calculated
as follows, 1/20MHz = 50ns, 1 line scan = 64ns therefore the number of samples
per line is 64ns/50ns=1280 samples. 128K of memory holds 131072 samples. Therefore
the total number of lines that can be stored is as follows, 131072/1280=102
Lines.
The design is divided
into 4 units. These are sampler hardware design, interface design, embedded
software design and PC display software design. The sampler is done in 2 phases.
Phase 1 is the development of a simple sampling device in order to be able
to work upon and experiment with the software at the earliest possible opportunity.
The second phase is done after the first phase and some software has been
designed and tested to such a degree that the system is shown to produce some
colour images. The second phase is done to improve performance and add some
extra functionality.
The interface design is
to allow data from the sampler circuit to be loaded into the microprocessor
and also allow processed data to be sent to the PC. The PC software is to
allow an image to be displayed.
4.2 Sampler Hardware Design
Method
4.2.1 Analogue to Digital
Converter
The analogue to digital
converter samples the input signal at 20MHz and has an 8bit resolution. The
output of the A-D converter is tri-state and only writes to the data bus when
the memory is high impedance.
The Analogue AD775 analogue
to digital converter (ADC) was chosen because the dynamic range of the ADC
can be configured. If a 0 to 1 voltage range is used the ADC gives 256 steps
of 3.9mV. If a 0 to 5 voltage range was used the ADC gives 256 steps of 19mV.
By selecting a dynamic range of 0 to 5 volts the ADC is insensitive to noise
of less than 19mV. However the video signal is only 1V p-p so it therefore
needs to be amplified of 5V p-p. This is done by using a video speed op-amp
with a gain of 5.
4.2.2 Op-Amp
The op-amp input circuit
performs 2 functions, one is to amplify the 1v p-p video signal to 5v p-p,
the other is to give the signal a DC offset so that the image data, the colour
burst and the sync pulse can be sampled, whilst allowing the image data to
occupy as much of the dynamic range as possible. This is done using a single
non-inverting op-amp circuit with adjustable gain and DC offset.
This circuit is an adapted
non-inverting op-amp circuit The change is the introduction of a no zero reference
voltage for the negative feedback potential divider. The 1K potential divider
is connected to the 10K potential divider, as shown below. The voltage produced
by the 1K potential divider can be said to be a constant reference voltage.
When viewed in the frequency domain the +V and 0V can be said to be short
circuited, resulting in a simple potential divider, thus giving a constant
frequency response.
In
amplifying the PAL signal a small amount of noise is added, however this noise
is trivial compared to the noise that could be picked up if a quantization
value of 3mV is used. 4.2.3 Memory and Counter To address 128KBytes
of memory a 17-bit synchronous address counter is required. This is done by
cascading five, 74F161 counters together, as indicated below. The clock is
common to all five I.C. counters and the RCO output is used as the count-enable
for the each successive I.C. A synchronous counter is essential because during
writing to the memory, any propagation delay glitches caused by a ripple counter
would cause data to be momentarily written to the wrong address, causing image
and line errors. The RCO of each counter is only asserted when the output
of the previous stage is equal to F16 (11112) and all
previous stages are equal to F16 (11112), thus ensuring
that higher order counters are not erroneously incremented when the previous
stage is F16 (11112) but the stages before that are
not yet F16 (11112). Ref[2]
4.2.4 Control Logic
4.2.4.1 Memory and
ADC bus synchronisation.
In order for the sampler
to be able to read or write, the memory and ADC must be synchronised so that
both devices to not try to write to the bus simultaneously. The ADC and the
memory have output enable pins, which control the tri-state buffers of the
output registers of each device. To ensure that the devices do not simultaneously
write to the data bus the control logic ensures that the output enable pins
of the devices are never asserted at the same instance. The output enable
pin of the memory will be referred to as /OE and the output enable pin of
the ADC will be referred to as /ADOE
4.2.4.2 Set-up, hold and
output times.
When sampling at 20MHz
propagation delay, set-up and hold-time are significant issues. The logic
must be designed so that all components work together and do not cause problems
for other components. The memory can be in write mode or read mode. When in
read mode the output of the device is enabled, this is done by setting the
output enable pin to zero (/OE=0).
When in write mode the
/OE pin is set to one to disable the output, otherwise the memory would try
to read and write at the same time, resulting in corrupt data. To write to
the device the write enable (/WE) pin must be set to zero, It is shown in
the timing diagram below that the /WE pin is set to zero for half of the time
available for each memory address set by the counter. This is to synchronise
the memory with the ADC.
The specifications for
the AD775 ADC show that the ADC writes on a rising clock input. The output
time can vary from 18ns to 30ns depending on the particular ADC. The memory’s
write logic must be designed so that this is accounted for. The write and
read cycle timing diagrams for the circuits to be designed are shown below.
By starting the ADC data
output process on the rising edge of the previous write cycle (T=0) valid
data can be guaranteed for at least 8ns during the write stage (T VALID).
From the above diagrams
it can be shown that /WE and /OW are never asserted together, nor are /OE
and /ADOE. The fast SRAM has a minimum set-up time of 8nS before the end of
the /WE stage
To keep the circuit synchronous
Q0 (LSB) from the cascaded counter is used for the ADC clock and the /WE for
the memory. During the read phase these signals are not required, thus two
clock cycles are required to increment the memory address. This is a minor
inconvenience but it significantly reduces the circuit complexity and propagation
delays.
During the read and write
phases different memory clocks are used. For writing a 40MHz clock is used,
giving a sampling rate of 20MHz and a /WE time of 25ns. For reading the DSK
interface logic produces pulses to increment the memory’s address every time
a memory read is made. The different clocks are selected using a multiplexor.
See appendix B1 for a
circuit diagram.
4.3 Phase 2 Hardware Design
4.3.1 Memory IC Chip Enable
Phase two has an identical
op-amp and ADC configuration and uses the same counter. The original design
was modified to allow three memory ICs to be addressed, increasing the memory
capacity to 3Mbit from 1Mbit. The modifications comprise a second state machine
that controls 3 memory chip select signals. Every time the main counter state
machine reaches its maximum value the chip select state machine is clocked,
selecting the next IC. Shown below is the truth table for the state machine.
