8.0 Discussion
8.1 ADC.
The device chosen has shown to produce good quality results, own to its wide configurable dynamic range. I had a only one problem with this device. The device would sometimes come unstable and start to heat up rapidly. This could be stopped by removing the power, the device would then operate as normal when started again. I have attributed problem to two possible things. 1) The device must be powered up and at a stable supply voltage before an alternating signal is applied, this could be because if the input voltage is momentarily higher that the supply voltage all p-n junctions will not be biased correctly. If the input voltage ever exceeds the supply voltage the device will go into a runaway mode. 2) If the output is momentarily connected to the active output of the memory under certain conditions then the device could go into its run away mode.
The first problem was tackled in the second hardware phase. The power supply driving op amp was taken from the supply for the ADC. The power supply is a switching one and requires a time constant to start producing current, therefore the ADC will have time to reach a constant supply before a signal is applied. This has shown to help but this problem has not completely gone away.
An anti aleasing filter was not used because PAL signals should have a limited bandwidth, typically 6.5MHz. Any frequencies greater 10MHz would be noise and since this noise must be greater then 19mV in the input of the ADC to be sampled I feel that this is not a problem as no such noise has ever been seen. See 1MHz sampled signal in graph n
8.2 Op-amp.
The gain and dc offset circuit has proved a success and allows fine adjustment of the input conditions. Due to the high frequency nature of the op-amp any capacitance and inductance in the feed back loop can cause oscillation. The device can be made to oscillate by removing the input signal and "playing" with the gain and offset pots, but however at the required configuration the device is stable. However if the device is on the verge of oscillation the signal could acquire extra sinusoidal components that would distort the image produced.
8.3 Phase 2
8.3.1 Chip select
Memory chip select the synchronous state machine used is a success, but it is the second version. The first one had asynchronous logic to decode binary values from a counter to produce the output signals. This was a 74161 counter with a 74138 decoder. When tested in ALTERA the simulator showed that the asynchronous circuit was not a problem, but when implemented a spurious pulse was produced when the counter changed from 01 to 10. A 11 was produced, causing the circuit to reset prematurely. This is evidence that simulators are not perfect. This was rectified by using the synchronous machine now used.
8.3.2 Power-Up
In order for the ALTERA I.C. to set up correct it was necessary to include a RC circuit to charge up and produce a clear pulse to reset the device. If this was not done then both the memory and the ADC would write to the same bus, causing the ADC to heat up.
It was found that the ALTERA circuit would lock up upon start up if certain input conditions were not met. This was not identified during the bench testing using low frequency clock inputs. I attribute this to a high frequency clock. The ALTERA I.C. is a 7064-15 the 15 denotes a 15ns propagation delay. By choosing an ALTERA I.C. with a 5ns delay this problem would not exist. The device could be made more stable by using state machine control unit instead of lots of logic gates and a single FDD. The design was not changed and the 7064-15 was kept because if the start up conditions were correct then the device would work correctly.
8.3.3 Blanking Period
After completion of the 2nd phase it was clear that the frame synchronisation was working correctly. The sampling process beginns at the beginning of each frame and this includes the 20 line blanking period. Since there is only sufficient memory to capture 330 lines waisting 20 lines allows 90% of the memory to store actual image data. This problerm could be be solved by introducing a delay after the sync pulse is recieved by the logic. The delay would cause the sampler to start sampling after a delay equivalent to 20 lines (xus)
8.3.4 Load line
The original load line program relied upon a zero value to end the process of loading data in to memory, however it was found that under certain conditions the algorithm would not stop loading data, over writing the rest of the program!. This was solved by counting the number of bytes loaded and then ending with a max number of bytes have been loaded. This made the entire program more stable.
8.4 Demodulation
This is the algorithm that produces the data to be displayed and therefore affects the quality of the image. The algorithm chosen was a sliding window with a response similar to a Fourier type filter with a 2.25 MHz cut off frequency. The results of a algorithms are so close that it is unlikely that results would be significantly improved by using the Fourier filter with differing coefficients. Adding the coefficients would result in a slower algorithm.
8.5 Limitations
8.5.1 Strange blue lines.
Upon obtaining color burst synchronization it was found that many small blue dots, present in the non synchronized image, aligned vertically to produce lines. The noise dots could not be seen in the monochrome image, therefore the dots could be noise added to the 4.4Mhz QAM signal or a property of the software.
The hardware was redesigned taking into consideration many noise reduction techniques, however the software was also re-written and I did not get a chance to do a fair comparison to see which on was causing the problem, However the I suspect that the problem was caused by the software due to the irregular positioning of the lines.
Shown below is an image with the blue lines
8.5.2 General image quality
Overall addition of small errors including possible noise in on input, quantisation errors with the ADC, errors with the algorithm such as the Q factor and phase locking method could all add up to reduce the quality of the final product.
Since the sampled image is still any small errors present in the transmission that would otherwise last only for a fraction of a second and not be seen may be digitised and displayed. In other words the frame rate also acts as a filter to remove spurious errors.
8.5.3. Compatibility with all PAL sources
The input circuit is sensitive to D.C. offset. Most PAL sources have a differing D.C. offset, therefore my project will only work with the PAL source it is calibrated for. By adding the circuit shown below the D.C offset wan be removed. This was not added to my project because it was not known about at the time of design.
I would have liked to perform some official tests using a calibrated PAL signal generator, however it was found that the signal from the generator had a significant negative bias and could not be corrected by the D.C. offset circuit. Given more time this would be corrected.